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Micrel
MIC4103/4104
C B
Vin
A typical layout of a synchronous Buck converter power
stage (Figure 11) is shown in Figure 12.
C VDD
HI
Vdd
Level
shift
HB
HO
High-Side
Fet
The circuit is configured as a synchronous buck power
stage. The high-side MOSFET drain connects to the input
supply voltage and the source connects to the switching
Low-Side Fet
HS
HS (switch) Node
Cin
node. The low-side MOSFET drain connects to the
switching node and its source is connected to ground. The
buck converter output inductor (not shown) would connect
LI
LO
to the switching node. The high-side drive trace, HO, is
routed on top of its return trace, HS, to minimize loop area
MIC4103
Vss
Figure 11. Synchronous Buck Converter Power Stage
Top Side
and parasitic inductance. The low-side drive trace LO is
routed over the ground plane which minimizes the
impedance of that current path. The decoupling capacitors,
C B and C VDD are placed to minimize trace length between
the capacitors and their respective pins. This close
placement is necessary to efficiently charge capacitor C B
when the HS node is low. All traces are 0.025” wide or
greater to reduce impedance. C IN is used to decouple the
high current path through the MOSFETs.
Bottom Side
Figure 12. Typical Layout of a Synchronous Buck Converter Power Stage
November 2010
17
M9999-110910-B
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